QF8 Hardware Cost Analysis

QF8 (QuakeFloat8) stores values as fixed-point log₂ codes, which means multiplication reduces to integer addition — an XOR for the sign bit and a 7-bit add for the log codes. This entry quantifies the hardware savings of this approach compared to conventional formats (INT8, FP8, FP16, FP32).

The analysis uses gate-level models anchored to published silicon data from Horowitz (ISSCC 2014, 45nm CMOS), Johnson (2018 ELMA ASIC, 28nm), and NVIDIA architecture whitepapers.

Multiply Path

The core advantage: where FP8 needs a 4×4 mantissa multiplier plus exponent logic, QF8 needs only a 7-bit adder.

Component	Gates	Area (μm², 7nm)
Sign XOR	1	0.04
7-bit CLA adder	50	2.0
Overflow/saturation detect	5	0.2
Zero detection	10	0.4
Total: multiply	66	2.6

Compare: INT8 8×8 multiplier = 400 gates; FP8 4×4 mantissa multiplier + exponent logic = 230 gates; FP16 11×11 multiplier = 850 gates.

QF8-Medium MAC Unit (Recommended Design Point)

After the log-domain multiply, the product must be converted to linear domain for accumulation (since addition is not cheap in log domain). This uses a 16-entry lookup table and a barrel shifter, followed by a Kulisch-style fixed-point accumulator: 32-bit intra-block + 48-bit inter-block for dot products up to ~4096 elements.

Component	Gates	Area (μm²)
Multiply path	66	2.6
exp2 LUT (16 × 12-bit ROM)	15	0.6
4-bit barrel shifter (12-bit data)	80	3.2
Sign-conditional negate	30	1.2
32-bit CLA accumulator (intra-block)	130	5.2
32-bit accumulator register	128	5.1
48-bit inter-block accumulator + reg	290	11.6
Block-pair reduction logic	40	1.6
Control/mux	35	1.4
Total	814	32.5

Master Comparison (per-MAC, 7nm, 1 GHz)

Metric	INT8	FP8 E4M3	FP16	FP32	QF8-Med
Gate count	750	1,350	2,400	5,950	814
Area (μm²)	30	54	96	238	33
Energy (pJ/MAC)	0.040	0.070	0.130	0.350	0.038
Pipeline stages	2	3	3	3–4	2

QF8-Medium is comparable to INT8 in area and power, but provides floating-point dynamic range (via the E8M0 block scale) and +6.6 dB better SQNR than FP8.

Savings Ratios

Metric	vs FP32	vs FP16	vs FP8	vs INT8
Area savings	86%	66%	40%	~parity (−8%)
Power savings	89%	71%	46%	~parity (+5%)

128×128 Systolic Array (7nm, 1 GHz)

Metric	INT8	FP8	FP16	FP32	QF8-Med
Compute area (mm²)	0.49	0.88	1.57	3.90	0.53
Total power (W)	0.68	1.19	2.21	5.93	0.65
TOPS/W	48.2	27.6	14.8	5.5	50.5

Break-Even Analysis

The multiplier gate count scales as O(n²) with bit-width, but the adder scales as O(n). So the log-domain advantage grows quadratically above the crossover point:

Bits	Net gate savings	vs INT-N
4	−82	1.5× worse
6	−50	1.2× worse
8	+64	0.92× (slight win)
12	+645	0.63×
16	+2,125	0.40×

Crossover at ~7–8 bits. Below 7 bits, the LUT and accumulator overhead exceeds multiplier savings. Above 8 bits, log-domain wins decisively. This confirms Johnson's 2018 finding that 16-bit ELMA achieves 41% power reduction over FP16.

The Honest Bottom Line

• QF8 vs FP32/FP16: Clear, large, robust win (3–10× savings)
• QF8 vs FP8: Moderate win (1.5–2×), real but not dramatic
• QF8 vs INT8: Approximately break-even (0.85–1.15×)
• The real value: 2× precision-per-octave at FP8-equivalent or better hardware cost